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Features
* Low-voltage and Standard-voltage Operation
- 1.8 (VCC = 1.8V to 5.5V)
* User-selectable Internal Organization
- 1K: 128 x 8 or 64 x 16 Three-wire Serial Interface 2 MHz Clock Rate (5V) Self-timed Write Cycle (5 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years * 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages * Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
* * * *
Three-wire Serial EEPROM
1K (128 x 8 or 64 x 16)
Description
The AT93C46D provides 1024 bits of serial electrically erasable programmable readonly memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C46D is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin miniMAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages. The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the DO pin. The Write cycle is completely self-timed, and no separate Erase cycle is required before Write. The Write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C46D is available in 1.8 (1.8V to 5.5V) version. Table 0-1.
Pin Name CS SK DI DO GND VCC ORG NC
AT93C46D
Pin Configurations
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization No Connect
CS SK DI DO CS SK DI DO
8-lead SOIC
1 2 3 4 8 7 6 5 VCC NC ORG GND
8-lead dBGA2
VCC NC ORG GND
8 7 6 5 1 2 3 4
CS SK D1 D0
Bottom View 8-lead PDIP
1 2 3 4 8 7 6 5 VCC NC ORG GND
8-lead Ultra Thin mini-MAP (MLP 2x3)
VCC NC ORG GND
8 7 6 5
CS SK 3 DI 4 DO
1 2
Bottom View 8-lead TSSOP
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
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1. Absolute Maximum Ratings*
Operating Temperature......................................-55C to +125C Storage Temperature .........................................-65C to +150C Voltage on Any Pin with Respect to Ground ........................................ -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Figure 1-1.
Block Diagram
Notes:
1. When the ORG pin is connected to VCC, the "x 16" organization is selected. When it is connected to ground, the "x 8" organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the "x 16" organization is selected. 2. For the AT93C46D, if the "x 16" organization is the mode of choice and pin 6 (ORG) is left unconnected, Atmel(R) recommends using AT93C46E device. For more details, see the AT93C46E datasheet.
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AT93C46D
Table 1-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) 1. This parameter is characterized and is not 100% tested. Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 1-2. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC ISB1 ISB2 ISB3 IIL IOL VIL1
(1)
Parameter Supply Voltage Supply Voltage Supply Voltage
Test Condition
Min 1.8 2.7 4.5 READ at 1.0 MHz
Typ
Max 5.5 5.5 5.5
Unit V V V mA mA A A A A A V
0.5 0.5 0.4 6.0 10.0 0.1 0.1
2.0 2.0 1.0 10.0 15.0 1.0 1.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4
Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
VCC = 5.0V VCC = 1.8V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC
WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V
VIH1(1) VIL2(1) VIH2
(1)
2.7V VCC 5.5V 1.8V VCC 2.7V 2.7V VCC 5.5V 1.8V VCC 2.7V IOL = 2.1 mA IOH = -0.4 mA IOL = 0.15 mA IOH = -100 A
-0.6
2.0
-0.6
VCC x 0.7
V V V
VOL1 VOH1 VOL2 VOH2 Note:
2.4 0.2 VCC - 0.2
V V
1. VIL min and VIH max are reference only and are not tested.
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Table 1-3. AC Characteristics Applicable over recommended operating range from TAI = -40C to + 85C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol fSK Parameter SK Clock Frequency Test Condition 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V Relative to SK 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V Min 0 0 0 250 250 1000 250 250 1000 250 250 1000 50 50 200 100 100 400 0 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 1.8V VCC 5.5V 0.1 1M 3 100 100 400 250 250 1000 250 250 1000 250 250 1000 100 150 400 5 Typ Max 2 1 0.25 Units MHz
tSKH
SK High Time
ns
tSKL
SK Low Time
ns
tCS
Minimum CS Low Time
ns
tCSS
CS Setup Time
ns
tDIS tCSH tDIH
DI Setup Time CS Hold Time DI Hold Time
Relative to SK Relative to SK Relative to SK
ns ns ns
tPD1
Output Delay to "1"
AC Test
ns
tPD0
Output Delay to "0"
AC Test
ns
tSV
CS to Status Valid
AC Test
ns
tDF tWP Endurance
(1)
CS to DO in High Impedance Write Cycle Time 5.0V, 25C
AC Test CS = VIL
ns ms Write Cycles
Note:
1. This parameter is ensured by characterization.
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AT93C46D
Table 1-4. Instruction Set for the AT93C46D
Op Code 10 00 11 01 00 00 00 Address x8 A6 - A0 11XXXXX A6 - A0 A6 - A0 10XXXXX 01XXXXX 00XXXXX x 16 A5 - A0 11XXXX A5 - A0 A5 - A0 10XXXX 01XXXX 00XXXX D7 - D0 D15 - D0 D7 - D0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address Write enable must precede all programming modes Erases memory location An - A0 Writes memory location An - A0 Erases all memory locations. Valid only at VCC = 4.5V to 5.5V Writes all memory locations. Valid only at VCC = 4.5V to 5.5V Disables all programming instructions
Instruction READ EWEN ERASE WRITE ERAL WRAL EWDS Note:
SB 1 1 1 1 1 1 1
The Xs in the address field represent DON'T CARE values and must be clocked.
2. Functional Description
The AT93C46D is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic "1") followed by the appropriate op code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic "0") precedes the 8- or 16-bit data output string. ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical "1" state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "1" at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "0" at DO indicates that programming is still in progress. A logic "1" indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the
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part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic "1" state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
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AT93C46D
3. Timing Diagrams
Figure 3-1. Synchronous Data Timing
s
Note:
1. This is the minimum SK period.
Table 3-1.
Organization Key for Timing Diagrams
AT93C46D (1K) I/O AN DN x8 A6 D7 x 16 A5 D15
Figure 3-2.
READ Timing
tCS
High Impedance
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Figure 3-3.
EWEN Timing
CS tCS
SK
DI
1
0
0
1
1
...
Figure 3-4.
EWDS Timing
CS tCS
SK
DI
1
0
0
0
0
...
Figure 3-5.
WRITE Timing
CS tCS
SK
DI
1
0
1
AN
...
A0
DN
...
D0
DO
HIGH IMPEDANCE
BUSY
READY
tWP
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AT93C46D
Figure 3-6. WRAL Timing(1)
CS tCS
SK
DI
1
0
0
0
1
...
DN
...
D0
DO
HIGH IMPEDANCE
BUSY READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 3-7.
ERASE Timing
tCS CS
CHECK STATUS STANDBY
SK
DI
1
1
1
AN AN-1 AN-2
...
A0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
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Figure 3-8.
ERAL Timing(1)
tCS CS
CHECK STATUS STANDBY
SK
DI
1
0
0
1
0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
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AT93C46D
4. AT93C46D Ordering Information
Ordering Code AT93C46D-PU (Bulk form only) AT93C46DN-SH-B AT93C46DN-SH-T
(1)
Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 (NiPdAu Lead finish) (NiPdAu Lead finish)
Package 8P3 8S1 8S1 8A2 8A2 8Y6 8U3-1 Die Sale
Operation Range
(2)
AT93C46D-TH-B(1) (NiPdAu Lead finish) AT93C46D-TH-T(2) (NiPdAu Lead finish) AT93C46DY6-YH-T(2) (NiPdAu Lead finish) AT93C46DU3-UU-T AT93C46D-W-11(3) Notes: 1. "-B" denotes bulk
(2)
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial (-40C to 85C)
2. "-T" denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, and dBGA2 = 5K per reel. 3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing.
Package Type 8P3 8S1 8A2 8U3-1 8Y6 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-ball, Die Ball Grid Array Package (dBGA2) 8-lead, 2.00 mm x 3.00 mm Body, 0.50mm Pitch, Ultra-Thin Mini-MAO, Dual No Lead Package. (DFN), (MLP 2x3mm) Options -1.8 Low Voltage (1.8V to 5.5V)
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5. Part Marking Scheme
5.1 AT93C46D 8-PDIP
Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark
TOP MARK
| | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 4 6 D 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot)
5.2
AT93C46D 8-SOIC
Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark
TOP MARK
| | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 4 6 D 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot)
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AT93C46D
5.3 AT93C46D 8-TSSOP
Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 4 6 D 1* |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| C 0 0 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: 2010 2011 2012 2013 WW = SEAL WEEK 02 04 :: :: = = : : Week Week :::: :::: 2 4 : ::
TOP MARK
50 = Week 50 52 = Week 52
5.4
AT93C46D 8-Ultra Thin Mini MAP
TOP MARK Y = YEAR OF ASSEMBLY |---|---|---| 4 6 D |---|---|---| H 1 |---|---|---| Y X X |---|---|---| * | Pin 1 Indicator (Dot) Y= 6: 7: 8: SEAL YEAR 2006 0: 2010 2007 1: 2011 2008 2: 2012 3: 2013 XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,...AX, AY, AZ)
9: 2009
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5.5
AT93C46D dBGA2
TOP MARK LINE 1-------> LINE 2-------> 46DU YMTC |<-- Pin 1 This Corner
Y 4: 5: 6:
= ONE DIGIT YEAR CODE 2004 7: 2007 2005 8: 2008 2006 9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBER TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK)
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AT93C46D
6. Package Information 8P3 - PDIP
1
E E1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A A1 b C COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE
D
D E1
SIDE VIEW
E e L
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C
R
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AT93C46D
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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8U3-1 - dBGA2
E
D
1.
b
PIN 1 BALL PAD CORNER
A1 A2 A
Top View
PIN 1 BALL PAD CORNER
Side View
4
1 (d1)
2
3
d
8 e
7
6
5
COMMON DIMENSIONS (Unit of Measure - mm) (e1) SYMBOL MIN 0.73 0.09 0.40 0.20 NOM 0.79 0.14 0.45 0.25 1.50 BSC 2.0 BSC 0.50 BSC 0.25 REF 1.00 BSC 0.25 REF MAX 0.85 0.19 0.50 0.30 2 NOTE
Bottem View
8 SOLDER BALLS
A A1 A2 b
1. This drawing is for general information only. 2. Dimension 'b' is measured at maximum solder ball diameter.
D E e e1 d d1
5/3/05
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2)
DRAWING NO. REV. PO8U3-1 B
R
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AT93C46D
8Y6 - MLP 2x3
A
D2
b (8X)
Pin 1 Index Area E2 E
Pin 1 ID L (8X)
D A2 A3 A1
e (6X) 1.50 REF.
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D E D2 E2 A A1 A2 A3 L e b 0.20 0.20 1.40 0.0 MIN NOM 2.00 BSC 3.00 BSC 1.50 0.02 0.20 REF 0.30 0.50 BSC 0.25 0.30 2 0.40 1.60 1.40 0.60 0.05 0.55 MAX NOTE
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground
10/16/07 REV. D
R
2325 Orchard Parkway San Jose, CA 95131
DRAWING NO. TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 Dual No Lead Package (DFN) ,(MLP 2x3)
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7. Revision History
Doc. Rev. 5193F 5193E Date 1/2008 11/2007 Comments Removed `preliminary' status Modified `max' value in AC Characteristics table Moved Pinout figure Added new feature for Die Sales Modified Ordering Information table layout Modified Park Marking Schemes Updated to new template Added Product Markup Scheme Added Technical email contact Corrected Figures 4 and 5. Added `Ultra Thin' description to 8-lead Mini-MAP package. Initial document release.
5193D
8/2007
5193C 5193C 5193B 5193A
6/2007 3/2007 2/2007 1/2007
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
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5193F-SEEPR-1/08

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